Semiconductor integrated circuits, such as memory chips, are becoming physically larger in area, and their operational speeds are becoming faster. One challenge in such circuits is to distribute signals, such as clock and data strobe signals, over distances that are characterized as long distances, at least long as compared to the time periods available for rise times, fall times, pulse widths, etc. With such circuits, it is becoming increasingly more important to maintain correct duty cycle on certain critical signals, such as clock and strobe signals, especially at high frequencies. However, when a single pulse is propagated through many driver receiver pairs, the duty cycle (e.g., as measured by the positive or negative pulse width) may change owing in part to differences in the characteristics of, for example, the p channel and n channel transistors that make up the drivers and receivers.
One such strobe signal is a DQS (“data strobe”) signal, and the timing of the DQS signal is especially important for double data rate (DDR) DRAMs in which both the rising and falling edges of the DQS signal are used to strobe data in and out of the DRAMs. Increases or decreases in duty cycle of the strobe, for any reason, will result in data clocked in early or late. At high frequencies, data that is clocked in early, may not be accurate since the voltages on the data lines many not have had time to settle to a level that is representative of the data value.
To facilitate signals driven into heavy and multiple loads, a design may employ intermediate drivers between the signal source and the ultimate loads in a “fan out” arrangement. Intermediate drivers tend to introduce duty cycle skew as well. For example, a 3 nanosecond pulse width might become more narrow than or wider than the original 3 nanoseconds when the pulse propagates through the intermediate driver. This may be due to the threshold (or trip point) at which the intermediate driver recognizes that a received signal has switched to another state (i.e., from “1” to “0” or from “0” to “1”). This may also be due to differences in the drive of the p channel and n channel transistors that constitute the intermediate driver (also called P-N drive imbalance). These effects cause a “1” to propagate differently than a “0”.
Use of differential signal intermediate drivers can eliminate these types of duty cycle errors, but a differential receiver is required at the destination. A differential input signal, which is actually a signal and its compliment, is applied to the input of the differential receiver. A cross point of the two signals that constitute input differential signal is defined to be the voltage at which the signals cross and have the exact same voltage at the exact same time. However, the cross point may not necessarily be midway between the signal high and signal low voltage. Instead, the cross-point of the input differential signal may be high or low relative to the design sensing threshold of the differential receiver. The high or low cross point may be caused by semiconductor process variations, P-N drive differences, temperature, VCC, common mode noise coupling equally into the differential signal, etc. The function of the differential receiver is to convert an input differential signal (in which the cross point may be high or low) into a centered output signal, either a differential output signal or a single ended output signal. The output signal of the differential driver, which must finally be used as a single ended signal for CMOS logic functions, has consistent timing for the final application. Duty cycle errors can be eliminated at the receiver since one signal goes high and the other signal goes low for both logic states and the cross point for each state contains the original duty cycle information.
Differential receivers have an additional advantage. Common mode bias that couples into the differential signal from stray signals or from supply noise can cause timing error (undesired delays) in single ended drivers. However, differential receivers eliminate these timing errors. Any coupling or supply noise that is common to both differential signals can be eliminated by the differential receiver. However, a problem remains with the use of known differential receivers. Known differential receivers are based on differential transistor pairs requiring a constant current source to propagate through either transistor of the differential pair. Thus, differential receivers consume a significant current whether or not differential signals are actually needed to be processed through the receiver at the particular time. In many applications it would be impractical to use as many differential pair receivers in critical clock paths as might otherwise be desired since a high standby current would be consumed.
Another problem is that this type of differential receiver has a different propagation delay depending on the voltage of the cross point of the differential input signals (as when a common mode voltage bias is coupled into the differential input signals). A varying propagation delay is unacceptable for critical timing paths, especially at high frequencies.
There is therefore the need for a differential receiver that can generate a differential output signal from a differential input signal while preserving the timing characteristics of the differential input signal.